Configuration FPGA Through XCF32P

Configuration FPGA Through XCF32P

Posted in the Xilinx Forum

Abdul Latheef A K

Perundurai, India

#1 Aug 4, 2010
I have my FPGA (Vertex 5)-XC5VLX110 connected to ISP-XCF32P in master serial mode. Downloading MCS to ISP done successfully through JTAG. But once I restart my system my ISP is not configuring my FPGA.
I checked the status of fallowing pins:
1. INIT goes high and stays at high.
2. PROG Pin goes high and stays high but
3. There is no BIT toggling in DIN pin
4. My CCLK continuously toggling at 2.73MHz
5. My DONE pin did not go high at all
6. My Status register is as fallows.
CRC error : 0
Decryptor security set : 0
DCM locked : 1
DCI matched : 1
End of startup signal from Startup block : 1
status of GTS_CFG_B : 1
status of GWE : 1
status of GHIGH : 1
value of MODE pin M0 : 0
value of MODE pin M1 : 0
Value of MODE pin M2 : 0
Internal signal indicates when housecleaning is completed: 1
Value driver in from INIT pad : 1
Internal signal indicates that chip is configured : 1
Value of DONE pin : 1
Indicates when ID value written does not match chip ID: 0
Decryptor error Signal : 0
System Monitor Over-Temperature Alarm : 0
startup_state[18] CFG startup state machine : 0
startup_state[19] CFG startup state machine : 0
startup_state[20] CFG startup state machine : 1
E-fuse program voltage available : 0
SPI Flash Type[22] Select : 0
SPI Flash Type[23] Select : 0
SPI Flash Type[24] Select : 1
CFG bus width auto detection result : 0
CFG bus width auto detection result : 0
Reserved : 0
BPI address wrap around error : 0
IPROG pulsed : 0
read back crc error : 0
Indicates that efuse logic is busy : 0

What could be the problem, please give me some solutions.

With Thanks,
Abdul Latheef A K

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