Noise Margin Calcumation for RLDRAM

Noise Margin Calcumation for RLDRAM

Posted in the Micron Technology Forum


Sunnyvale, CA

#1 Feb 16, 2012

I wanted to understand how to calculate Noise Margin for the RLDRAM3 part (datasheet is at the URL =

The calculation would take into account all worst case voltage values as indicated in the datasheet.

Thank you.

Since: Feb 12

San Jose, CA

#2 Feb 17, 2012
The basic concept of the noise margin is interconnection between RLDRAM and controllers.
The followings are for general noise margin concept of CMOS inverter.
NML=VIL-VOL(noise margin for low input)
NMH=VOH-VIH(noise margin for high input)
RLDRAM has Vref level for single-Ended Input signals which should be considered with the above noise margin and also has dual differential input clocks which slew rate of clock signals is more important than other single-Ended Input signals because the trip point is reference of dual clocks. To improve interface signals, RLDRAM has ODT option of input pins and ZQ option of output pins which protect overshoot/undershoot of tR/tF.
All of the above options with worst case voltage values of datasheet could be simulated and tested for noise margin.
If you would like to need more detail information I would like to recommend you visit ISSI site and review ISSI datasheet or contact with ISSI Marketing.

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